open! Core0

let keywords s = String.split_lines s |> List.map ~f:String.strip

let verilog =
  (* Taken from latest Verilog spec IEEE Std 1364-2005 (page 364, reserved keywords) *)
  keywords
    {| always
       and
       assign
       automatic
       begin
       buf
       bufif0
       bufif1
       case
       casex
       casez
       cell
       cmos
       config
       deassign
       default
       defparam
       design
       disable
       edge
       else
       end
       endcase
       endconfig
       endfunction
       endgenerate
       endmodule
       endprimitive
       endspecify
       endtable
       endtask
       event
       for
       force
       forever
       fork
       function
       generate
       genvar
       highz0
       highz1
       if
       ifnone
       incdir
       include
       initial
       inout
       input
       instance
       integer
       join
       large
       liblist
       library
       localparam
       macromodule
       medium
       module
       nand
       negedge
       nmos
       nor
       noshowcancelled
       not
       notif0
       notif1
       or
       output
       parameter
       pmos
       posedge
       primitive
       pull0
       pull1
       pulldown
       pullup
       pulsestyle_onevent
       pulsestyle_ondetect
       rcmos
       real
       realtime
       reg
       release
       repeat
       rnmos
       rpmos
       rtran
       rtranif0
       rtranif1
       scalared
       showcancelled
       signed
       small
       specify
       specparam
       strong0
       strong1
       supply0
       supply1
       table
       task
       time
       tran
       tranif0
       tranif1
       tri
       tri0
       tri1
       triand
       trior
       trireg
       unsigned
       use
       uwire
       vectored
       wait
       wand
       weak0
       weak1
       while
       wire
       wor
       xnor
       xor |}
;;

let vhdl =
  keywords
    {| abs
       access
       after
       alias
       all
       and
       architecture
       array
       assert
       attribute
       begin
       block
       body
       buffer
       bus
       case
       component
       configuration
       constant
       disconnect
       downto
       else
       elsif
       end
       entity
       exit
       file
       for
       function
       generate
       generic
       group
       guarded
       if
       impure
       in
       inertial
       inout
       is
       label
       library
       linkage
       literal
       loop
       map
       mod
       nand
       new
       next
       nor
       not
       null
       of
       on
       open
       or
       others
       out
       package
       port
       postponed
       procedure
       process
       pure
       range
       record
       register
       reject
       return
       rol
       ror
       select
       severity
       signal
       shared
       sla
       sli
       sra
       srl
       subtype
       then
       to
       transport
       type
       unaffected
       units
       until
       use
       variable
       wait
       when
       while
       with
       xnor
       xor |}
;;

(* From the OCaml source code: src/parsing/lexer.mll:38 *)
let ocaml =
  keywords
    {| and
       as
       assert
       begin
       class
       constraint
       do
       done
       downto
       else
       end
       exception
       external
       false
       for
       fun
       function
       functor
       if
       in
       include
       inherit
       initializer
       lazy
       let
       match
       method
       module
       mutable
       new
       nonrec
       object
       of
       open
       or
       private
       rec
       sig
       struct
       then
       to
       true
       try
       type
       val
       virtual
       when
       while
       with
       lor
       lxor
       mod
       land
       lsl
       lsr
       asr |}
;;

let systemverilog =
  keywords
    {| accept_on
       export
       ref
       alias
       extends
       restrict
       always_comb
       extern
       return
       always_ff
       final
       s_always
       always_latch
       first_match
       s_eventually
       assert
       foreach
       s_nexttime
       assume
       forkjoin
       s_until
       before
       global	s_until_with
       bind
       iff
       sequence
       bins
       ignore_bins
       shortint
       binsof
       illegal_bins
       shortreal
       bit
       implies
       solve
       break
       import
       static
       byte
       inside
       string
       chandle
       int
       strong
       checker
       interface
       struct
       class
       intersect
       super
       clocking
       join_any
       sync_accept_on
       const
       join_none
       sync_reject_on
       constraint
       let
       tagged
       context
       local
       this
       continue
       logic
       throughout
       cover
       longint
       timeprecision
       covergroup
       matches
       timeunit
       coverpoint
       modport
       type
       cross
       new
       typedef
       dist
       nexttime
       union
       do
       null
       unique
       endchecker
       package
       unique0
       endclass
       packed
       until
       endclocking
       priority
       until_with
       endgroup
       program
       untypted
       endinterface
       property
       var
       endpackage
       protected
       virtual
       endprogram
       pure
       void
       endproperty
       rand
       wait_order
       endsequence
       randc
       weak
       enum
       randcase
       wildcard
       eventually
       randsequence
       with
       expect
       reject_on
       within |}
  @ verilog
;;
